com.sun.electric.tool.io.output
Class Verilog

java.lang.Object
  extended by com.sun.electric.tool.io.output.Output
      extended by com.sun.electric.tool.io.output.Topology
          extended by com.sun.electric.tool.io.output.Verilog

public class Verilog
extends Topology

This is the Simulation Interface tool.


Nested Class Summary
 
Nested classes/interfaces inherited from class com.sun.electric.tool.io.output.Topology
Topology.CellAggregateSignal, Topology.CellNetInfo, Topology.CellSignal, Topology.MyCellInfo, Topology.Visitor
 
Nested classes/interfaces inherited from class com.sun.electric.tool.io.output.Output
Output.OutputCellInfo, Output.WriteJELIB
 
Field Summary
static Variable.Key VERILOG_BEHAVE_FILE_KEY
          key of Variable holding file name with Verilog.
static Variable.Key VERILOG_CODE_KEY
          key of Variable holding verilog code.
static Variable.Key VERILOG_DECLARATION_KEY
          key of Variable holding verilog declarations.
static Variable.Key VERILOG_DEFPARAM_KEY
          key of Variable holding verilog defparams.
static Variable.Key VERILOG_EXTERNAL_CODE_KEY
          key of Variable holding verilog code that is external to the module.
static Variable.Key VERILOG_PARAMETER_KEY
          key of Variable holding verilog parameters.
static Variable.Key VERILOG_TEMPLATE_KEY
          key of Variable holding verilog templates.
static Variable.Key WIRE_TYPE_KEY
          key of Variable holding verilog wire time.
 
Fields inherited from class com.sun.electric.tool.io.output.Topology
topCell
 
Fields inherited from class com.sun.electric.tool.io.output.Output
dataOutputStream, printWriter, quiet, stringWriter
 
Method Summary
protected  boolean canParameterizeNames()
          Method to tell whether the topological analysis should mangle cell names that are parameterized.
protected  void done()
          Abstract method called after traversal
static Cell findCell(java.lang.String verilogName, View preferredView)
          Find a cell corresponding to the Verilog-style name of a cell.
protected  java.lang.String getGlobalName(Global glob)
          Method to return the proper name of a Global signal
protected  java.lang.String getGroundName(Network net)
          Method to return the proper name of Ground
protected  java.lang.String getPowerName(Network net)
          Method to return the proper name of Power
protected  java.lang.String getSafeCellName(java.lang.String name)
          Method to adjust a cell name to be safe for Verilog output.
protected  java.lang.String getSafeNetName(java.lang.String name, boolean bus)
          Method to adjust a network name to be safe for Verilog output.
protected  Netlist.ShortResistors getShortResistors()
          Tell the Hierarchy enumerator how to short resistors
static java.lang.String getVerilogSafeName(java.lang.String name, boolean isNode, boolean isBus)
           
protected  boolean isAggregateNameGapsSupported()
          Abstract method to decide whether aggregate names (busses) can have gaps in their ranges.
protected  boolean isAggregateNamesSupported()
          Method to report that aggregate names (busses) ARE used.
protected  boolean isCaseSensitive()
          Abstract method to decide whether netlister is case-sensitive (Verilog) or not (Spice).
protected  boolean isLibraryNameAlwaysAddedToCellName()
          Method to report that library names ARE always prepended to cell names.
protected  boolean isNetworksUseExportedNames()
          Method to report that export names DO take precedence over arc names when determining the name of the network.
protected  boolean isSeparateInputAndOutput()
          Method to report whether input and output names are separated.
protected  boolean skipCellAndSubcells(Cell cell)
          If the netlister has requirments not to netlist certain cells and their subcells, override this method.
protected  void start()
          Abstract method called before hierarchy traversal
protected  void writeCellTopology(Cell cell, Topology.CellNetInfo cni, VarContext context, Topology.MyCellInfo info)
          Method to write cellGeom
static void writeVerilogFile(Cell cell, VarContext context, java.lang.String filePath)
          The main entry point for Verilog deck writing.
 
Methods inherited from class com.sun.electric.tool.io.output.Topology
enterCell, enumerateLayoutView, getCellNetInfo, getUniqueCellName, isChooseBestExportName, isShortExplicitResistors, isShortResistors, maxNameLength, parameterizedName, unIndexedName, validateSkippedCell, writeCell, writeCell
 
Methods inherited from class com.sun.electric.tool.io.output.Output
closeBinaryOutputStream, closeStringsOutputStream, closeTextOutputStream, emitCopyright, exportCellCommand, getAreaToPrint, openBinaryOutputStream, openStringsOutputStream, openTextOutputStream, saveJelib, setContinuationString, setOutputWidth, writeCell, writeLibrary, writePanicSnapshot, writeWidthLimited
 
Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait
 

Field Detail

VERILOG_CODE_KEY

public static final Variable.Key VERILOG_CODE_KEY
key of Variable holding verilog code.


VERILOG_DECLARATION_KEY

public static final Variable.Key VERILOG_DECLARATION_KEY
key of Variable holding verilog declarations.


VERILOG_PARAMETER_KEY

public static final Variable.Key VERILOG_PARAMETER_KEY
key of Variable holding verilog parameters.


VERILOG_EXTERNAL_CODE_KEY

public static final Variable.Key VERILOG_EXTERNAL_CODE_KEY
key of Variable holding verilog code that is external to the module.


WIRE_TYPE_KEY

public static final Variable.Key WIRE_TYPE_KEY
key of Variable holding verilog wire time.


VERILOG_TEMPLATE_KEY

public static final Variable.Key VERILOG_TEMPLATE_KEY
key of Variable holding verilog templates.


VERILOG_DEFPARAM_KEY

public static final Variable.Key VERILOG_DEFPARAM_KEY
key of Variable holding verilog defparams.


VERILOG_BEHAVE_FILE_KEY

public static final Variable.Key VERILOG_BEHAVE_FILE_KEY
key of Variable holding file name with Verilog.

Method Detail

getVerilogSafeName

public static java.lang.String getVerilogSafeName(java.lang.String name,
                                                  boolean isNode,
                                                  boolean isBus)

writeVerilogFile

public static void writeVerilogFile(Cell cell,
                                    VarContext context,
                                    java.lang.String filePath)
The main entry point for Verilog deck writing.

Parameters:
cell - the top-level cell to write.
context - the hierarchical context to the cell.
filePath - the disk file to create.

start

protected void start()
Description copied from class: Topology
Abstract method called before hierarchy traversal

Specified by:
start in class Topology

done

protected void done()
Description copied from class: Topology
Abstract method called after traversal

Specified by:
done in class Topology

skipCellAndSubcells

protected boolean skipCellAndSubcells(Cell cell)
Description copied from class: Topology
If the netlister has requirments not to netlist certain cells and their subcells, override this method.

Overrides:
skipCellAndSubcells in class Topology

writeCellTopology

protected void writeCellTopology(Cell cell,
                                 Topology.CellNetInfo cni,
                                 VarContext context,
                                 Topology.MyCellInfo info)
Method to write cellGeom

Specified by:
writeCellTopology in class Topology

getSafeCellName

protected java.lang.String getSafeCellName(java.lang.String name)
Method to adjust a cell name to be safe for Verilog output.

Specified by:
getSafeCellName in class Topology
Parameters:
name - the cell name.
Returns:
the name, adjusted for Verilog output.

getPowerName

protected java.lang.String getPowerName(Network net)
Method to return the proper name of Power

Specified by:
getPowerName in class Topology

getGroundName

protected java.lang.String getGroundName(Network net)
Method to return the proper name of Ground

Specified by:
getGroundName in class Topology

getGlobalName

protected java.lang.String getGlobalName(Global glob)
Method to return the proper name of a Global signal

Specified by:
getGlobalName in class Topology

isNetworksUseExportedNames

protected boolean isNetworksUseExportedNames()
Method to report that export names DO take precedence over arc names when determining the name of the network.

Specified by:
isNetworksUseExportedNames in class Topology

isLibraryNameAlwaysAddedToCellName

protected boolean isLibraryNameAlwaysAddedToCellName()
Method to report that library names ARE always prepended to cell names.

Specified by:
isLibraryNameAlwaysAddedToCellName in class Topology

isAggregateNamesSupported

protected boolean isAggregateNamesSupported()
Method to report that aggregate names (busses) ARE used.

Specified by:
isAggregateNamesSupported in class Topology

isAggregateNameGapsSupported

protected boolean isAggregateNameGapsSupported()
Abstract method to decide whether aggregate names (busses) can have gaps in their ranges.

Specified by:
isAggregateNameGapsSupported in class Topology

isSeparateInputAndOutput

protected boolean isSeparateInputAndOutput()
Method to report whether input and output names are separated.

Specified by:
isSeparateInputAndOutput in class Topology

isCaseSensitive

protected boolean isCaseSensitive()
Abstract method to decide whether netlister is case-sensitive (Verilog) or not (Spice).

Specified by:
isCaseSensitive in class Topology

getSafeNetName

protected java.lang.String getSafeNetName(java.lang.String name,
                                          boolean bus)
Method to adjust a network name to be safe for Verilog output. Verilog does permit a digit in the first location; prepend a "_" if found. Verilog only permits the "_" and "$" characters: all others are converted to "_". Verilog does not permit nonnumeric indices, so "P[A]" is converted to "P_A_" Verilog does not permit multidimensional arrays, so "P[1][2]" is converted to "P_1_[2]" and "P[1][T]" is converted to "P_1__T_"

Specified by:
getSafeNetName in class Topology
Parameters:
bus - true if this is a bus name.

getShortResistors

protected Netlist.ShortResistors getShortResistors()
Tell the Hierarchy enumerator how to short resistors

Overrides:
getShortResistors in class Topology

canParameterizeNames

protected boolean canParameterizeNames()
Method to tell whether the topological analysis should mangle cell names that are parameterized.

Overrides:
canParameterizeNames in class Topology

findCell

public static Cell findCell(java.lang.String verilogName,
                            View preferredView)
Find a cell corresponding to the Verilog-style name of a cell. See getVerilogName(com.sun.electric.database.hierarchy.Cell).

Parameters:
verilogName - the Verilog-style name of the cell
preferredView - the preferred cell view. Schematic if null.
Returns:
the cell, or null if not found