com.sun.electric.tool.io.output
Class GenerateVHDL

java.lang.Object
  extended by com.sun.electric.tool.io.output.Output
      extended by com.sun.electric.tool.io.output.Topology
          extended by com.sun.electric.tool.io.output.GenerateVHDL

public class GenerateVHDL
extends Topology

This is the VHDL generation facility.


Nested Class Summary
 
Nested classes/interfaces inherited from class com.sun.electric.tool.io.output.Topology
Topology.CellAggregateSignal, Topology.CellNetInfo, Topology.CellSignal, Topology.MyCellInfo, Topology.Visitor
 
Nested classes/interfaces inherited from class com.sun.electric.tool.io.output.Output
Output.OutputCellInfo, Output.WriteJELIB
 
Field Summary
 
Fields inherited from class com.sun.electric.tool.io.output.Topology
topCell
 
Fields inherited from class com.sun.electric.tool.io.output.Output
dataOutputStream, filePath, printWriter, quiet, stringWriter
 
Constructor Summary
GenerateVHDL()
           
 
Method Summary
protected  boolean canParameterizeNames()
          Method to tell the netlister to mangle cell names that are parameterized.
static java.util.List<java.lang.String> convertCell(Cell cell)
          Method to convert a cell to a list of strings with VHDL in them.
protected  void done()
          Abstract method called after traversal
protected  java.lang.String getGlobalName(Global glob)
          Method to return the proper name of a Global signal
protected  java.lang.String getGroundName(Network net)
          Method to return the proper name of Ground (just use whatever name is there)
protected  java.lang.String getPowerName(Network net)
          Method to return the proper name of Power (just use whatever name is there)
protected  java.lang.String getSafeCellName(java.lang.String name)
          Method to adjust a cell name to be safe for Verilog output.
protected  java.lang.String getSafeNetName(java.lang.String name, boolean bus)
          Method to adjust a network name to be safe for VHDL output.
protected  Netlist.ShortResistors getShortResistors()
          Method to tell the netlister how to short resistors
protected  boolean isAggregateNameGapsSupported()
          Method to decide whether aggregate names (busses) can have gaps in their ranges.
protected  boolean isAggregateNamesSupported()
          Method to report that aggregate names (busses) are not used.
protected  boolean isCaseSensitive()
          Method to tell the netlister to be case-sensitive.
protected  boolean isLibraryNameAlwaysAddedToCellName()
          Method to report that library names are not always prepended to cell names.
protected  boolean isNetworksUseExportedNames()
          Method to tell the netlister that export names DO take precedence over arc names when determining the name of the network.
protected  boolean isSeparateInputAndOutput()
          Method to tell netlister not to separate input and output names (this module does more detailed separation).
protected  boolean skipCellAndSubcells(Cell cell)
          Method to tell the netlister to deal with all Cells.
protected  void start()
          Method to start the output.
protected  void writeCellTopology(Cell cell, Topology.CellNetInfo cni, VarContext context, Topology.MyCellInfo info)
          Method to write one level of hierarchy.
 
Methods inherited from class com.sun.electric.tool.io.output.Topology
enterCell, enumerateLayoutView, getCellNetInfo, getUniqueCellName, isChooseBestExportName, isShortExplicitResistors, isShortResistors, maxNameLength, parameterizedName, unIndexedName, validateSkippedCell, writeCell, writeCell
 
Methods inherited from class com.sun.electric.tool.io.output.Output
closeBinaryOutputStream, closeStringsOutputStream, closeTextOutputStream, emitCopyright, exportCellCommand, getAreaToPrint, openBinaryOutputStream, openStringsOutputStream, openTextOutputStream, saveJelib, setContinuationString, setOutputWidth, writeCell, writeLibrary, writePanicSnapshot, writeWidthLimited
 
Methods inherited from class java.lang.Object
clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait
 

Constructor Detail

GenerateVHDL

public GenerateVHDL()
Method Detail

convertCell

public static java.util.List<java.lang.String> convertCell(Cell cell)
Method to convert a cell to a list of strings with VHDL in them.

Parameters:
cell - the Cell to convert.
Returns:
a list of strings with VHDL in them (null on error).

start

protected void start()
Method to start the output. Writes the header.

Specified by:
start in class Topology

done

protected void done()
Description copied from class: Topology
Abstract method called after traversal

Specified by:
done in class Topology

writeCellTopology

protected void writeCellTopology(Cell cell,
                                 Topology.CellNetInfo cni,
                                 VarContext context,
                                 Topology.MyCellInfo info)
Method to write one level of hierarchy.

Specified by:
writeCellTopology in class Topology

getSafeCellName

protected java.lang.String getSafeCellName(java.lang.String name)
Method to adjust a cell name to be safe for Verilog output.

Specified by:
getSafeCellName in class Topology
Parameters:
name - the cell name.
Returns:
the name, adjusted for Verilog output.

skipCellAndSubcells

protected boolean skipCellAndSubcells(Cell cell)
Method to tell the netlister to deal with all Cells.

Overrides:
skipCellAndSubcells in class Topology

getPowerName

protected java.lang.String getPowerName(Network net)
Method to return the proper name of Power (just use whatever name is there)

Specified by:
getPowerName in class Topology

getGroundName

protected java.lang.String getGroundName(Network net)
Method to return the proper name of Ground (just use whatever name is there)

Specified by:
getGroundName in class Topology

getGlobalName

protected java.lang.String getGlobalName(Global glob)
Method to return the proper name of a Global signal

Specified by:
getGlobalName in class Topology

isNetworksUseExportedNames

protected boolean isNetworksUseExportedNames()
Method to tell the netlister that export names DO take precedence over arc names when determining the name of the network.

Specified by:
isNetworksUseExportedNames in class Topology

isLibraryNameAlwaysAddedToCellName

protected boolean isLibraryNameAlwaysAddedToCellName()
Method to report that library names are not always prepended to cell names.

Specified by:
isLibraryNameAlwaysAddedToCellName in class Topology

isAggregateNamesSupported

protected boolean isAggregateNamesSupported()
Method to report that aggregate names (busses) are not used.

Specified by:
isAggregateNamesSupported in class Topology

isAggregateNameGapsSupported

protected boolean isAggregateNameGapsSupported()
Method to decide whether aggregate names (busses) can have gaps in their ranges.

Specified by:
isAggregateNameGapsSupported in class Topology

isSeparateInputAndOutput

protected boolean isSeparateInputAndOutput()
Method to tell netlister not to separate input and output names (this module does more detailed separation).

Specified by:
isSeparateInputAndOutput in class Topology

isCaseSensitive

protected boolean isCaseSensitive()
Method to tell the netlister to be case-sensitive.

Specified by:
isCaseSensitive in class Topology

getShortResistors

protected Netlist.ShortResistors getShortResistors()
Method to tell the netlister how to short resistors

Overrides:
getShortResistors in class Topology

canParameterizeNames

protected boolean canParameterizeNames()
Method to tell the netlister to mangle cell names that are parameterized.

Overrides:
canParameterizeNames in class Topology

getSafeNetName

protected java.lang.String getSafeNetName(java.lang.String name,
                                          boolean bus)
Method to adjust a network name to be safe for VHDL output.

Specified by:
getSafeNetName in class Topology